TFRST=0, RFRST=0, DRES=0
FIFO Control Register
| DRES | Receive data ready error select bit 0 (0): reception data full interrupt (SCIn_RXI) 1 (1): receive error interrupt (SCIn_ERI) |
| TTRG | Transmit FIFO data trigger number |
| TFRST | Transmit FIFO Data Register Reset 0 (0): It is invalid. It does not affect the operation. 1 (1): The number of data stored in Transmit-FIFO (TDR register) are made 0 |
| RTRG | Receive FIFO data trigger number |
| RFRST | Receive FIFO Data Register Reset 0 (0): It is invalid. It does not affect the operation. 1 (1): The number of data stored in Receive-FIFO(RDR register) are made 0 |
| RSTRG | RTS Output Active Trigger Number Select |